1. Field of the Invention
The invention relates to a method of deposition on a wafer, and more particularly to a method of deposition on a wafer as applicable to the process of shallow trench isolation (STI), in which deposition is performed on a wafer with a machine WJ-1000 or WJ-999.
2. Description of the Related Art
STI is a general method for device isolation. It is often used to form shallow trenches between devices, after which a field oxide layer used to isolate devices is then formed by depositing an insulator. Referring to FIG. 1A, the formation of the field oxide region forms a pad oxide layer 10 and a silicon nitride layer 12 on a substrate 1. The substrate 1 is defined to form a STI by photolithography. Then, an oxide layer 14 used to isolate the devices is deposited over the substrate 1 and chemical mechanical polishing (CMP) is performed to planarize the STI to remove the excess portion of oxide layer 14. However as CMP is performed, a recess 15 occurs in the oxide layer 14a because the uniformity is not really good, as shown in FIG. 1B. The nitride layer 12 and the pad oxide layer 10 are then removed to accomplish a structure to serve as a field oxide region of device as illustrated in FIG. 1C.
In the process as described above, wet etching is used to remove the pad oxide layer 10, in which process hydrofluoric acid solution is employed as an etchant. During isotropic etching, the surface of the oxide layer 14b adjacent the substrate 10 is over-retched due to erosion by the hydrofluoric acid. A concave space 16 is thus produced at the sidewalls of the trench.
Additionally, a sacrificial oxide layer used to protect the surface of the substrate is typically formed over the surface of the substrate after forming the device isolation region. The sacrificial oxide layer is removed by hydrofluoric acid solution and overretching may still cause a concave space on the oxide layer adjacent to the surface of the substrate.
When the semiconductor device is completed, the accumulation of charges occurring in the concave space formed on the oxide layer adjacent to the substrate reduces the threshold voltage of the transistor and produces the abnormal sub-threshold current associated with the "kink effect". Occurrence of the kink effect impairs device and circuit performance and is thus undesirable.
In the prior art, the STI process is always performed in a 2-PASS procedure by a WJ-1000 or WJ-999 machine. FIG. 2 is a top view of a WJ-1000 or WJ-999 machine. Although the WJ-1000 or WJ-999 machine is able to use deposition to thoroughly cover wafers up to a size of 4, 5 or 6 inches, the WJ-1000 or WJ-999 machine cannot completely cover 8-inch wafers by deposition. Therefore the main deposition coverage 30 is centralized on the middle region of the wafer as shown in FIG. 3A, where the region beside the middle region is deposited as a thin region 32. As the 2-PASS process is performed on the 8-inch wafer, the deposition thickness for four corners on the wafer is especially thin such that the uniformity within the wafer is not quite superior. The thinner deposition corners 34 are as shown in FIG. 3B. This situation as described above exerts a huge influence in the following process. For example, the four corners are over-polished as CMP is finished and a serious recess, such as recess 14 in FIG. 1B, is thus produced on the wafer during the process of CMP. Similarly, the kink effect becomes more obvious and the yield of wafer production is lower. In the conventional 2-PASS deposition method, the error between the maximum and the minimum thickness detected with 49 probes by the WJ-1000 or WJ-999 machine is in a range of about 800-850 .ANG.. Moreover, if a 1-PASS, 3-PASS or 5-PASS is performed, the uniformity becomes poor due to the asymmetrical, odd-numbered deposition. It is undesirable in the semiconductor process that the recess becomes more and more serious in subsequent CMP.